The present invention relates generally to semiconductor device manufacture and, particularly, to improvements in plasma planarization of semiconductor device layers and the formation of interlevel interconnect locations. More specifically, the present invention relates to an improved photoresist aperture profile and the process for creating the improved aperture profile.
As integrated circuit geometries increase in complexity and decrease in dimensions it becomes increasingly important to provide component layers with smooth or planar surface topographies. Steps often inhibit proper application of additional device layers. In the fabrication of multilevel devices it is generally necessary to form apertures through one device layer to an underlying layer. The sidewall height and angle of these apertures is generally too abrupt for good metal coverage.
To reduce sidewall angles and soften edges, previous fabrication processes have included high temperature "reflow" techniques. The substrate and glass thereon would be heated to temperatures where the glass softens and starts to melt. The substrate, however, maintains its stability at these temperatures. Unfortunately, reflow techniques have often proved unsatisfactory where metal is used. To insulate these paths, oxide layers are typically applied between them. These oxide layers substantially conform to the underlying surface topography. Thus, subsequent paths applied directly to the oxide would not have a planar base surface. Without a planar base surface, designing complex, multi-layer circuits become extremely difficult. Attempts to apply reflow techniques to the oxide layers are not succesful. Temperatures high enough to soften the oxide and cause it to flow will also cause underlying metal paths to melt or peel off adjacent layers or alloy with the silicon. This results in silicon surface pits and resultant device failures. Further, such high temperature processing is often not reliable and will generally enlarge device dimensions and promote poor feature size control which subsequently causes loss of device packing density.
Recently, low temperature plasma etching techniques for smoothing rough and irregular surface topographies have been developed. These are often referred to as "plasma planarization" or "plasma filing". As seen in the sectional view of FIG. 1, plasma planarization typically involves the use of a sacrificial layer 10 which is applied over rough topography 20 of insulating layer 30. Rough topography 20 may, for example, result from conformity of insulating layer 30 to metal path 40 formed on insulative layer 50 of substrate base 60. Prior research and experimentation have been directed toward achieving a planar surface 15 on sacrificial layer 10. This multi-layered product is subjected to plasma etching in a gas environment to completely remove sacrifical layer 10 and portions of insulating layer 30. Sacrificial layer 10 is etched away at the same rate as the material of insulating layer 30. As a result, the topography of relatively smooth surface 15 can be replicated on the surface 20 of insulating layer 30 without detrimentally affecting metal path 40.
Such plasma planarization techniques have been used to smooth surfaces of several materials, including polysilicon, nitrides, and various glasses. A variety of sacrificial layers have also been used, including photoresists, polyimide, and nitrides. Unfortunately, while previous plasma planarization techniques may be suitable for fabrication of some larger, less detailed integrated circuits, they do not produce surfaces which are sufficiently planar for many smaller and more complex circuit devices.
Further difficulties also arise with the relatively narrow processing constraints of these prior techniques. According to these prior techniques, the ratio of the etch rates of the sacrificial layer to the underlying insulating layer must, as nearly as possible, be unity if the topography of surface 15 is to be properly replicated. Even the smallest deviation from a unity ratio is considered undesirable.
A solution of the above difficulties has been described in copending U.S. Ser. No. 591,597, now U.S. Pat. No. 4,515,652, entitled "Plasma Sculpturing With A Non-Planar Sacrificial Layer" and owned by the assignee of the present invention. The copending application describes a method of plasma planarization of the surface topography of a substrate layer wherein a sacrificial layer, having an etch rate substantially different from the etch rate of the substrate layer, is applied to the surface topography of that substrate layer. The sacrificial and substrate layers are then plasma etched to remove the sacrificial layers and portions of the substrate layer. The ratio of substrate to sacrificial layer etch rate can be controlled to compensate for non-planar surface features of the sacrificial layer such that the resulting substrate surface topography is planar. Control of this etch rate ratio is accomplished by selecting appropriate materials forming the sacrificial layer for a given plasma environment and by selecting the appropriate plasma environment for a given material forming the sacrifical layer. This process is a "low temperature" process which is suitable for multilayer devices which may have previously applied metal contacts or lines that could be damaged by temperatures high enough, for instance, to cause photoresist to melt or flow.
The present invention relates to an improved method of fabricating semiconductor devices, and more particularly to the fabrication of devices incorporating multilevel interconnect technology.
A desirable process for the fabrication of multilevel interconnect semiconductor devices would provide smoothing of the interlevel dielectric, etching of vias which will be used for interlevel connections and tapering of the vias to improve interconnect step coverage into the vias without requiring high temperatures. The present invention relates to a novel and easily implemented method of tapering the via by providing a tapering of the via photoresist which is transferred to the oxide during the erosion of the photoresist. Prior methods of tapering the photoresist have not been easily controlled thus it was difficult if not impossible to obtain uniformity in the manufactured end products.
Gwozdz, U.S. Pat. No. 4,451,326 issued May 29, 1984 is illustrative of the attempts being made to provide an improved via profile for facilitating good metal coverage in the via. The multi-step process described by Gwozdz is cumbersome and only serves to reduce the step height into the via. Gwozdz recognized the need to provide improved metal coverage but was not able to provide a commercially feasible solution.
Non-vertical sidewalls have previously resulted in an uncontrolled manner from excessive heating during bake out of photoresist causing it to melt and flow into the aperture. Notwithstanding the desire to improve metal step coverage, it has been found that photomask sidewall shaping at melting or near-melting temperatures is nearly impossible to controllably reproduce and generally, that the melt and flow of photoresist can be more detrimental than beneficial in a high-yield semiconductor manufacture process. A description of this technique is provided by Kern and Rosier, "Advances in Deposition Processes for Passivation Films" J. Vac. Sci. Technical, Vol. 14, No. 5, September/October 1977.
It is also noted that photoresist erosion sometimes occurs during etching of the aperture of the underlying oxide. While this erosion can result in a tapered photoresist aperture sidewall, such uncontrolled erosion does not provide the controlled taper desired for consistent and reliable semiconductor manufacture where high yield is dependent on tapered photoresist sidewalls. Consistency and reliability can only be provided if the photoresist is provided with a preselected and controlled taper.
It is an object of the present invention to provide a tapered profile to a photoresist opening.
It is a further object of the present invention to provide a tapered photoresist opening without requiring any increase in the number of process steps beyond those ordinarily required for forming a photoresist opening.
These and other objects are accomplished according to the present invention which allows a taper to be imparted to a photoresist opening by rounding the peripheral edge of the opening and then faceting the inner surface of the photoresist opening. The rounding of the peripheral edge of the photoresist opening results in the exposure of a surface along which a facet will be preferentially etched during an ensuing etch step. Thus, the exposed inner surface of the opening will be tapered at the angle defined by the preferential etch characteristics of the photoresist and the etch process utilized. In order for the photoresist to exhibit the desired faceting characteristics during the plasma etch, it is necessary to alter the photoresist by a pretreatment comprising exposure to a suitable energy source.
The opening of a preferentially profiled aperture in a photoresist without any increase in the number of process steps is accomplished pursuant the present invention as described herein with reference to the accompanying drawings.